This invention relates to voltage regulators. In particular, this invention relates to switch-mode voltage regulators.
Switch-mode regulators, or switching regulators as they are commonly known, are typically used as voltage regulators because they exhibit higher efficiency than an equivalent linear regulator circuit at heavy loads. A typical switching regulator operates by repeatedly turning a power switch fully on and then fully off, generating a pulse-width modulated signal that is averaged to the final voltage with an inductor.
For simplicity, the present invention is particularly described in a step-down converter embodiment. Nevertheless, the invention is not limited to this particular embodiment and, in fact, may be implemented on any suitable switching regulator. The basic invention, as well as alternative implementations of the invention, will be discussed in more detail below.
FIG. 1 shows a basic, conventional switching regulator system 100. FIG. 1 includes an oscillated clock 102 of a pulse-width modulated (PWM) system, an inverter 104, a flip-flop 106, a switch 108, an inductor 110, a current source 112, an output capacitor 114, a resistor divider 116 and 118, a voltage feedback amplifier 120 (or any suitable amplifier), a feedback capacitor 122, and a current comparator 124 (or any other suitable comparator). It should be noted that inverter 104 preferably causes the PWM switch to turn ON coincident with the end of the ON cycle of clock 102. At least in this respect, the clock and the PWM switch are preferably out of phase with one another.
In general, a switching regulator generates an output voltage proportional to the input voltage, with the proportionality set by the duty cycle of the pulse width signal at the power switch. Accordingly, the switch duty cycle (the percentage of the total switching cycle that the power switch is ON) of a PWM step-down voltage regulator is determined by:
d=VOUT/VIN wherein:
d is duty cycle;
VOUT is the regulator output voltage; and
VIN is the regulator input voltage.
As the input voltage of the power supply system becomes smaller—e.g., when a battery's voltage drops as a result of usage of the battery—, the switching regulator is forced to operate at a very high clock cycle rate to maintain a substantially constant VOUT. As the clock cycle rate increases, and, consequently, the clock cycle time decreases, it becomes difficult to achieve a very high and/or a very low switch-ON duty cycle as operating conditions may at times require.
FIGS. 2A and 2B show clock-oscillated signals generated by the clock 102 of PWM system 100 shown in FIG. 1.
FIG. 3 shows a conventional clock oscillator 300 of the PWM system shown in FIG. 1. Clock oscillator includes a charging current source 302, an oscillating capacitor 304, a first comparator 306, a switch 308, a discharging current sink 310, and a second comparator 312. Also indicated are Vramp and VN (which is compared to Vramp using comparator 306 for opening and closing switch 308).
The most common method of generating constant repeating switching clock cycles for the clock oscillator 300 of the PWM system is by charging oscillator capacitor 304 with a current using charging source 302 until the capacitor voltage is charged up to the preset level VTH (Voltage Threshold High) and resetting the oscillator to VTL (Voltage Threshold Low) after the capacitor reaches VTH.
The clock cycle time T=T1 +T2 as shown in FIG. 2B may be obtained using the following equations:
                              T          ⁢                                          ⁢          1                =                  Cosc                                    (              Icharge              )                        ×                          (              VTH              )                                                                        T          ⁢                                          ⁢          2                =                  Cosc                                    (              Idischarge              )                        ×                          (              VTH              )                                          
Cosc is the capacitance of the oscillator;
Icharge is the charge current;
Idischarge is the discharging current;
VTH is the Voltage Threshold—High; and
VTL is the Voltage Threshold—Low.
Preferably, this oscillator reset process takes a fraction of the total clock cycle time.
In a basic PWM regulator, the switching cycle of the PWM switch 108 begins when switch 308 turns ON at the beginning of T1 (see FIGS. 2A, 2B and 3). The switch-ON duration is determined by the duty cycle which is a function of VIN and VOUT of PWM switching regulator 300, as described above. The switch-ON duration may end at any time during T1. If switch 108 has not been switched OFF by the beginning of T2 and switch 308 is not allowed to turn ON longer than one clock cycle (no cycle skipping) then, switch 308 is typically forced to turn OFF at the beginning of T2 when the oscillator resets.
As the switching frequency increases, each clock cycle becomes so short that it is critical to keep T2 as short as practically possible for high maximum switch duty cycle. In practice, T2 is usually determined by the power transistor switch 108 (see FIG. 1) turn-OFF/ON time.
Typical maximum duty cycle with no cycle skipping ranges from 90% to 95%. When the VIN/VOUT condition of the PWM regulator requires a duty cycle that is higher than the oscillator maximum duty cycle can provide, the output loses regulation. This condition may occur, for example, when a step down converter has a VIN (Input Voltage) that is very close to VOUT (Output Voltage).
In order not to lose output regulation when a higher duty cycle is required, the most common prior art approach is to skip cycles by not turning OFF switch 308 at T2. This method extends the switch-ON time of the PWM longer.
An example of cycle skipping is as follows: a 10 microsecond clock cycle time with OFF time T2 of 1 microsecond and maximum ON time T1 of 9 microsecond gives maximum duty cycle of 90%. If the regulator operation requires a 91% duty cycle, then it follows there will be one non-reset cycle with 10 microseconds ON time for every 9 reset cycles at T2 with 9 microseconds ON time each. This one cycle skip in every 10 cycles on the average has duty cycle of 91%.
One problem with this approach is that it often generates troublesome audible noise because of a low frequency modulation phenomenon associated with the cycle skipping.
Another prior art method uses an open loop comparator approach. The system remains in the oscillator-based constant frequency PWM mode until the OFF time reaches the preset level. To extend the duty cycle, the system then switches to the fixed off time variable frequency mode with no oscillator involved. The disadvantage of this is that a frequency hysteresis is needed to switch back to the other mode when the duty cycle reduces and the abrupt mode change sometimes cause system frequency instability.
It would be desirable to increase the duty cycle of the clock oscillator of a PWM system operating in a voltage regulator without skipping cycles and without abrupt mode changes.